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Research Article | Open Access |

An Improved Squaring Circuit for Binary Numbers

Author 1: Kabiraj Sethi Author 2: Rutuparna Panda
International Journal of Advanced Computer Science and Applications (IJACSA) · Vol. 3, No. 2 · Published 2012 · Cited by 28

DOI: https://doi.org/10.14569/IJACSA.2012.030220

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Abstract

In this paper, a high speed squaring circuit for binary numbers is proposed. High speed Vedic multiplier is used for design of the proposed squaring circuit. The key to our success is that only one Vedic multiplier is used instead of four multipliers reported in the literature. In addition, one squaring circuit is used twice. Our proposed Squaring Circuit seems to have better performance in terms of speed.

Keywords

Vedic mathematics VLSI binary multiplication hardware design VHDL.

How to Cite this Article

Sethi, K., & Panda, R. (2012). An Improved Squaring Circuit for Binary Numbers. International Journal of Advanced Computer Science and Applications, 3(2). https://doi.org/10.14569/IJACSA.2012.030220

Sethi, Kabiraj, and Rutuparna Panda. "An Improved Squaring Circuit for Binary Numbers." International Journal of Advanced Computer Science and Applications, vol. 3, no. 2, 2012, https://doi.org/10.14569/IJACSA.2012.030220.

@article{Sethi2012,
  title     = {An Improved Squaring Circuit for Binary Numbers},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {3},
  number    = {2},
  year      = {2012},
  publisher = {The Science and Information Organization},
  author    = {Kabiraj Sethi and Rutuparna Panda},
  doi       = {10.14569/IJACSA.2012.030220},
  url       = {https://doi.org/10.14569/IJACSA.2012.030220}
}

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